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Balerion's avatar
Balerion
Icon for Occasional Contributor rankOccasional Contributor
9 months ago
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Nios-V alt_epcq_controller_write() Problem

Hi, I have a flash on my custom board which is MT25QU01G. The flash is connected to Nios-V/g with Epcq Controller. I am trying to erase, write, read sectors from flash. Before write and erase I unlo...
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Nios Architecture
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  • ShoH_Altera's avatar
    ShoH_Altera
    9 months ago

    Hi Balerion,

    Regading to avl_mem slave:

    If you also place avl_mem slave in Peripheral Region, you can use the current altera_epcq_controller.c file as is.

    However, you may want to place avl_mem slave in cacheable (non-Peripheral) region to take advantage of the cache for read accesses.  In that case, cache maintenance needed for flash memory write operation in Nios V/g system.  Here is a code example (= not fully validated) to achieve this attached (please replace the file extension from ".txt" to ".c").   At the end of the alt_epcq_controller_write_block() function, cache flush function call and error checking are added.

    Thanks,
    ShoH

Balerion's avatar
Balerion
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Hi,

I'm using Quartus Pro 25.1.1 and My Fpga is Arria-10. 

Thanks,

Balerion

ShoH_Altera's avatar
ShoH_Altera
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Thanks for the info.  I'll check if I can prepare a similar set-up.  
 
Regarding flash controller, are you using Serilal Flash Controller, not Serial Flash Controller II ?

And just to be sure, you are assigning avl_csr address of the flash controller in non-cached address region, right?

Regards,
Sho

  • Balerion's avatar
    Balerion
    Icon for Occasional Contributor rankOccasional Contributor
    9 months ago

    Hi,

    I am using Serial Flash Controller such that the generated bsp includes "altera_epcq_controller.h" It would include "altera_epcq_controller2.h" if I use Serial Flash Controller II as much as I know. Could you please tell me how to look for the cached and non-cached addresses . My ram starts from base address 0x00000000 to 0x3FFFFFFF and my epcq flash avl memory starts from base address 0x40000000 and my avl csr base starts from 0x48050040. I don't know which addresses are cached or not.

    Thanks,

    Balerion

    • ShoH_Altera's avatar
      ShoH_Altera
      Icon for Occasional Contributor rankOccasional Contributor
      9 months ago

      I see that you are using Serial Flash Controller.
      Cached and non-cached regions( = peripheral regions) are specified in your HW design (Nios V IP configuration in PlatformDesigner).   If the HW design was not designed by you, please check with your HW designer.  (I think UART or JTAG-UART is used in your design and the UART works as expected.  If so, the UART registers should already be correctly located in a peripheral region. )
      https://www.intel.com/content/www/us/en/docs/programmable/726952/25-1/memory-configurations-tab.html

      Regards,
      Sho

      • Balerion's avatar
        Balerion
        Icon for Occasional Contributor rankOccasional Contributor
        9 months ago

        Hi,

        I looked at memory configuration page and see that my Data cache and Instruction cache sizes are 4KiloBytes. All my Peripheral regions and Tightly coupled memory settings are 0. My jtag uart base address is 0x48050060. I am able to use jtag uart without a problem. Is there anything you want me to check?

        Thanks,

        Balerion