Forum Discussion
Nios-V alt_epcq_controller_write() Problem
- 9 months ago
Hi Balerion,
Regading to avl_mem slave:
If you also place avl_mem slave in Peripheral Region, you can use the current altera_epcq_controller.c file as is.
However, you may want to place avl_mem slave in cacheable (non-Peripheral) region to take advantage of the cache for read accesses. In that case, cache maintenance needed for flash memory write operation in Nios V/g system. Here is a code example (= not fully validated) to achieve this attached (please replace the file extension from ".txt" to ".c"). At the end of the alt_epcq_controller_write_block() function, cache flush function call and error checking are added.
Thanks,
ShoH
Hi Balerion
I'll try to reproduce the issue.
Can you share Quartus version and FPGA device that you are using with?
Regards,
Sho
- Balerion9 months ago
Occasional Contributor
Hi,
I'm using Quartus Pro 25.1.1 and My Fpga is Arria-10.
Thanks,
Balerion
- ShoH_Altera9 months ago
Occasional Contributor
Thanks for the info. I'll check if I can prepare a similar set-up.
Regarding flash controller, are you using Serilal Flash Controller, not Serial Flash Controller II ?
And just to be sure, you are assigning avl_csr address of the flash controller in non-cached address region, right?Regards,
Sho- Balerion9 months ago
Occasional Contributor
Hi,
I am using Serial Flash Controller such that the generated bsp includes "altera_epcq_controller.h" It would include "altera_epcq_controller2.h" if I use Serial Flash Controller II as much as I know. Could you please tell me how to look for the cached and non-cached addresses . My ram starts from base address 0x00000000 to 0x3FFFFFFF and my epcq flash avl memory starts from base address 0x40000000 and my avl csr base starts from 0x48050040. I don't know which addresses are cached or not.
Thanks,
Balerion