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Altera_Forum
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15 years ago

NIOS not reading the right FIFO value

Hello guys, i made a 32bits DCFIFO using the megawizard.

I made this wrapper to increment the fifo value by each second (my fifo is running at 50mhz) 

begin
        contador <= contador +1;
        valid <= 0;
        wrclk <= 0;
           if(usedw == 6'b100000)
            begin
                valid <= 1;
            end
            if(contador == 50000000)
            begin
                data_in <= data_in + 1;
                wrclk <=1;
                contador <= 0;
            end
end
base    fifo_inst (
    .data ( data ),
    .rdclk ( rdclk ),
    .rdreq ( rdreq ),
    .wrclk ( wrclk ),
    .wrreq ( 1 ),
    .q ( q ),
    .wrusedw ( usedw )
    );

When my fifo is half full my valid goes to 1 and then i start to read from the fifo with this routine 


            printf("content of fifo\n");
            for ( i=0;i<32;i++)
           {
            printf("%d: %x\n",i,IORD(FIFOWRAPPER_0_BASE,0));
           }

i should get the values 1,2,3,4,5,6,7,8,9,A etc..

However i am getthing this values: 

bash-3.1$ nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster ", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
loop start
waiting valid from fifo .................:
content of fifo:
0: 1
1: 3
2: 5
3: 7
4: 9
5: b
6: d
7: f
8: 11
9: 13
10: 15
11: 17
12: 19
13: 1b
14: 1d
15: 1f
16: 20
17: 20
18: 20
19: 20
20: 20
21: 20
22: 20
23: 20
24: 20
25: 20
26: 20
27: 20
28: 20
29: 20
30: 20
31: 20
END

That's very weird. Can someone enlight me pleas?

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    First your read and write clocks should be your system clock, and you should just use the rdreq and wrreq signals to control the fifo read and writes. Using generated signals as clock can lead to problems such as extra clock cycles due to glitches.

    Then it seems that each read that you do from the software is creating two read cycles on the fifo. Could you show us your HDL code that reads from the FIFO?

    You can also use signaltap probes on your component to see what is going on.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Ok, now i am controlling the WRREQ when i want to write something and my WRCLK is my sysclk. But the problem persists.

    I changed my clock to sys clock (100 mhz), the problem persists.

    I am leaving rdreq to avalon (it works right? It is a read signal) also rdclk is at my avalon as a clk signal

    I am reading from fifo via software only, my rdreq and my q signals are at the Avalon as read and readdata respectivly

    Thanks for the help, looking forward for your response.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If i change the synchronization of the fifo in the megawizard to show-ahead mode instead of normal mode (data becomes available before rdreq) i get the pairs 

    
bash-3.1$ nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster ", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
loop start
0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:content of fifo:before DMA operation
0: 2
1: 4
2: 6
3: 8
4: a
5: c
6: e
7: 10
8: 12
9: 14
10: 16
11: 18
12: 1a
13: 1c
14: 1e
15: 20
16: 0
17: 0
18: 0
19: 0
20: 0
21: 0
22: 0
23: 0
24: 0
25: 0
26: 0
27: 0
28: 0
29: 0
30: 0
31: 0

    weird...
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Ok IT'S WORKING!!

    I changed the Read wait property on the Avalon interface from 1 to 0 (luck shot) and now i can read everything right.

    HOWEVER

    When it goes throught the DMA i can only read 8 bits per time, why is that?

    Simple for: 

    
loop start
0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:content of fifo:before DMA operation
0: 0
1: 1
2: 2
3: 3
4: 4
5: 5
6: 6
7: 7
8: 8
9: 9
10: a
11: b
12: c
13: d
14: e
15: f
16: 10
17: 11
18: 12
19: 13
20: 14
21: 15
22: 16
23: 17
24: 18
25: 19
26: 1a
27: 1b
28: 1c
29: 1d
30: 1e
31: 1f
FIM

    FOR in a onchip mem after going throught the DMA (FIFO->DMA->ONCHIP) 

    
content of onchip:before DMA operation
0: 33333333
1: 33333333
2: 33333333
3: 33333333
4: 33333333
5: 33333333
6: 33333333
7: 33333333
8: 0
9: 0
10: 0
11: 0
12: 0
13: 0
14: 0
15: 0
16: 0
17: 0
18: 0
19: 0
20: 0
21: 0
22: 0
23: 0
24: 0
25: 0
26: 0
27: 0
28: 0
29: 0
30: 0
31: 0
32: 0
33: 0
Transfer successful!
content of onchip:after DMA operation
0: 0
1: 1
2: 2
3: 3
4: 4
5: 5
6: 6
7: 7
8: 0
9: 0
10: 0
11: 0
12: 0
13: 0
14: 0
15: 0
16: 0
17: 0
18: 0
19: 0
20: 0
21: 0
22: 0
23: 0
24: 0
25: 0
26: 0
27: 0
28: 0
29: 0
30: 0
31: 0
32: 0
33: 0
1:testing fifo & onchip : dma operation
content of onchip:before DMA operation
0: 33333333
1: 33333333
2: 33333333
3: 33333333
4: 33333333
5: 33333333
6: 33333333
7: 33333333
8: 0
9: 0
10: 0
11: 0
12: 0
13: 0
14: 0
15: 0
16: 0
17: 0
18: 0
19: 0
20: 0
21: 0
22: 0
23: 0
24: 0
25: 0
26: 0
27: 0
28: 0
29: 0
30: 0
31: 0
32: 0
33: 0
Transfer successful!
content of onchip:after DMA operation
0: 8
1: 9
2: a
3: b
4: c
5: d
6: e
7: f
8: 0
9: 0
10: 0
11: 0
12: 0
13: 0
14: 0
15: 0
16: 0
17: 0
18: 0
19: 0
20: 0
21: 0
22: 0
23: 0
24: 0
25: 0
26: 0
27: 0
28: 0
29: 0
30: 0
31: 0
32: 0
33: 0
FIM
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    If you have a look at the timing diagrams generated in the component editor, you would see that the read signal is active during two cycles in its default configuration. The intended behaviour is that on the first cycle the component reads the read request and the address, and gives the result on the readdata vector to be read on the next cycle. But you are right that if you put the fifo in show-ahead mode then you can reduce the read to one cycle. The FMax will probably be lower though.

    To help you with your new problems, you'll have to give more details about what you are doing, what results you expect and what you got instead.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I was expecting to have the same result i had when reading the fifo with a normal for (32 sequential numbers), instead the DMA is only transfering 8 bits per time to the OnChipMem (and always in the same 8 slots).

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It works.. i changed the LEN value from 32 to 128.

    Why did it work? I am just trying my luck changing everything 

    
/* Post the transmit request */
    if ((rc = alt_dma_txchan_send (txchan,
            tx_data,
            128,
            NULL,
            NULL)) < 0)
    {
        printf ("Failed to post transmit request, reason = %i\n", rc);
        //exit (1);
    }
    /* Post the receive request */
    if ((rc = alt_dma_rxchan_prepare (rxchan,
            rx_buffer,
            128,
            txrxDone,
            NULL)) < 0)

    before it was 32 (since i want 32 bytes per transaction)

    Final result.. 

    
bash-3.1$ nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster ", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
loop start
0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:testing fifo & onchip : dma operation
content of onchip:before DMA operation
0: 64
1: 65
2: 66
3: 67
4: 68
5: 69
6: 6a
7: 6b
8: 6c
9: 6d
10: 6e
11: 6f
12: 70
13: 71
14: 72
15: 73
16: 74
17: 75
18: 76
19: 77
20: 78
21: 79
22: 7a
23: 7b
24: 7c
25: 7d
26: 7e
27: 7f
28: 80
29: 81
30: 82
31: 83
32: 0
33: 0
Transfer successful!
content of onchip:after DMA operation
0: 0
1: 1
2: 2
3: 3
4: 4
5: 5
6: 6
7: 7
8: 8
9: 9
10: a
11: b
12: c
13: d
14: e
15: f
16: 10
17: 11
18: 12
19: 13
20: 14
21: 15
22: 16
23: 17
24: 18
25: 19
26: 1a
27: 1b
28: 1c
29: 1d
30: 1e
31: 1f
32: 0
33: 0
FIM

    Thanks for the help!!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I recommend that you only allow the FIFO to be read when it's not empty. And if a read occurs when the FIFO is empty you assert waitrequest back to the fabric. Otherwise you may end up reading garbage out of the FIFO or cause it to underflow.