NIOS not reading the right FIFO value

Ok, now i am controlling the WRREQ when i want to write something and my WRCLK is my sysclk. But the problem persists.

I changed my clock to sys clock (100 mhz), the problem persists.

I am leaving rdreq to avalon (it works right? It is a read signal) also rdclk is at my avalon as a clk signal

I am reading from fifo via software only, my rdreq and my q signals are at the Avalon as read and readdata respectivly

Thanks for the help, looking forward for your response.