NIOS not reading the right FIFO value

First your read and write clocks should be your system clock, and you should just use the rdreq and wrreq signals to control the fifo read and writes. Using generated signals as clock can lead to problems such as extra clock cycles due to glitches.

Then it seems that each read that you do from the software is creating two read cycles on the fifo. Could you show us your HDL code that reads from the FIFO?

You can also use signaltap probes on your component to see what is going on.