NIOS not reading the right FIFO value

If you have a look at the timing diagrams generated in the component editor, you would see that the read signal is active during two cycles in its default configuration. The intended behaviour is that on the first cycle the component reads the read request and the address, and gives the result on the readdata vector to be read on the next cycle. But you are right that if you put the fifo in show-ahead mode then you can reduce the read to one cycle. The FMax will probably be lower though.