Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Nios II won't work after uploaded to the board

Greetings,

I have a Nios II design that i've built from scratch, mainly following instructions on the book Rapid Prototyping of Digital System. It compiles without errors (but several warnings, 139 to be exact).

The problem is when I upload it to the board (Altera DE2 board with Cyclone II FPGA chip). The segments of HEX Displays light up randomly and some red leds too.

I already checked thoroughly all pin assignments, remade all of them more than once, and made unassigend pins be As Inputs, tristated.

After checking the pins, the random leds and HEX segments, turned off.

I both cases, when I try to upload my linux distribution to the board (after uploading the processor), it says that it can't unpause the processor.

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

The reset pin is assigned to a pushbutton.

I'm using Quartus 10.1 and Nios2EDS 10.1

Thanks in advance

Bruno

12 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    @Daixiwen

    My primary reference designs don't contain sdc files. Looking at the output of the TimeQuest, after compilation, it indeed shows warnings about clock not being defined. I'll look at other reference designs to learn what to do.

    @Thormodo

    I didn't know about the PLL reset signal, I will add it in MegaWizzard and wire it properly.

    The SOPC generates one .sdc file, called cpu.sdc (my Nios II module is named cpu]. It does not contain the line pointed by you, I'll add and see what happens.

    Unfortunately, my notebook keyboard is broken and I'll take a while until I fix it to continue my work.

    Meanwhile, I have other doubt. My SDRAM address is at 0x1000 0000. But when I upload a image to the board (using nios2-download utility] it starts downloading at 0xD000 0000. Is it a physical address or a logical one? Does it have to do with the Verify phase failing? Is there a place where I can define the address to upload? Or is it defined in the image file? (it is a uClinux image].

    Thanks for your help so far, and your patience. I'm really beginning to learn these things.

    Best regards,

    Bruno
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    It finally worked!

    I used TimeQuest Wizard to add the lines that Thormodo cited and added the reset pin to the PLL. It worked like a charm :)

    As for the questions I asked, I found that the address is defined in the image generated. I believe that it is a logical address rather than a physical one, but not sure yet.

    It didn't uncompress the linux image, but I was expecting it due to low memory availability. Now I'll fight the uClinux-dist rather than the Quartus II.

    Thank you all again for your patience. As soon as I get everything to work, I will write a short tutorial and maybe an entry to the wiki.

    Best regards

    Bruno