Honored Contributor
Honored Contributor@Daixiwen
My primary reference designs don't contain sdc files. Looking at the output of the TimeQuest, after compilation, it indeed shows warnings about clock not being defined. I'll look at other reference designs to learn what to do. @Thormodo I didn't know about the PLL reset signal, I will add it in MegaWizzard and wire it properly. The SOPC generates one .sdc file, called cpu.sdc (my Nios II module is named cpu]. It does not contain the line pointed by you, I'll add and see what happens. Unfortunately, my notebook keyboard is broken and I'll take a while until I fix it to continue my work. Meanwhile, I have other doubt. My SDRAM address is at 0x1000 0000. But when I upload a image to the board (using nios2-download utility] it starts downloading at 0xD000 0000. Is it a physical address or a logical one? Does it have to do with the Verify phase failing? Is there a place where I can define the address to upload? Or is it defined in the image file? (it is a uClinux image]. Thanks for your help so far, and your patience. I'm really beginning to learn these things. Best regards, Bruno
