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Altera_Forum
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14 years ago

NIOS II SBT Configuration with EPCS Controller

Hi All,

I have a basic NIOS II system with a EPCS Controller used for booting. I have successfully flashed the EPCS device and on power-up the FPGA configures and the NIOS boots.

However, I can now no longer 'Run' the system from Software Build Tools. The Console output is: 

Using cable "USB-Blaster ", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x00009840: verified
Initializing CPU cache (if present)
OK
Downloading 00004020 ( 0%)
Downloading 00007124 (93%)
Downloading 00008800 (99%)
Downloaded 13KB in 0.2s (65.0KB/s)
Verifying 00004020 ( 0%)
Verifying 00007124 (93%)
Verifying 00008800 (99%)
Verify failed between address 0x8800 and 0x881F
Leaving target processor paused

0x8800 is the base address of the EPCS Controller. Surely the SBT should only be writing to the onchip RAM (address 0x4000 to 0x7FFF)?

Another concern is how the processor will be reset. The reset vector is set to the EPCS controller base address within QSYS. However, will the SBT Run Configuration reset to the base of the on-chip RAM?

The qsys, spocinfo and bsp settings files are attached

Any ideas?

Thanks

Andy

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    ...Another concern is how the processor will be reset. The reset vector is set to the EPCS controller base address within QSYS. However, will the SBT Run Configuration reset to the base of the on-chip RAM?...

    --- Quote End ---

    Inside SOPC builder GUI (Q11.1 SP2) it appears there is no way to set the reset vector to the EPCS base address. Epcs is absent in the reset vector pull-down menu of the NIOS II processor.

    In Qsys it seems to be possible but only by entering the absolute address of the EPCS flash "manually". Not by menu selection. This lack of pull-down menu selection does make me suspicious as to the validity of the method.

    is setting reset=absolute base address of the epcs (a part of) the way to direct nios to boot from the epcs flash it in qsys?

    Thanks for hints.

    And out of curiosity - because I'm switched to Qsys now - how would you possibly do this in SOPC builder?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Are you sure the Nios II instruction master is connected to the EPCS controller and not just tho data mastor? If you don't see the controller in the reset menu it means there is a problem with the way all the components are connected, or at least in how SOPC builder / QSys sees those connections.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Are you sure the Nios II instruction master is connected to the EPCS controller and not just tho data mastor?..

    --- Quote End ---

    spot on! The EPCS was only connected to the data master. Did once a similar thing with a dma where a bus was missing. One day I will learn it.

    The board is working nicely out of boot now running FreeRTOS. I would be embarrassed to tell how much time I have wasted on this boot problem. Well, at least I have had the occasion to read some application notes and manuals!

    A million thanks for your help.

    henning
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    I have now found the final solution to the problem with the run command:

    There is a parameter in the settings.bsp file, ALT_ALLOW_CODE_AT_RESET, that must be set to 0 in order to get the flash bootloader code to work with the Run command.

    I have not found how to set this parameter from the BSP-editor, so just edit the bsp file directly.

    --- Quote End ---

    Thank you. This resolved a similar issue I was having. I had my reset vector in EPCS flash. I could flash my sof and elf (converted to jic) and run from flash with no problem. However, when I tried to connect with JTAG I would get "Verify failed" at my reset vector offset. Changing ALT_ALLOW_CODE_AT_RESET to zero in my bsp settings resolved this issue for me.

    I was able to find this setting in the BSP Editor (I am using SBT 12.1sp1). Go to BSP Editor -> Main -> Settings -> Advanced -> hal -> linker -> allow_code_at_reset. Disable checkbox. Hope this helps future users.

    -JQ