Forum Discussion
New ContributorNios-II Resets with PIO command
I am developing an application using the Nios-II embedded CPU. It utilizes multiple PIO ports, configured as inputs and outputs. I have one in particular that is being very troublesome. Everytime I write to it, it causes the Nios core to reboot.
It resides, in memory, in the same range as the other PIO registers. Nothing seems to jump out that is different from this register than from the others.
Has anyone seen this and possibly some suggestions as to the cause?
Thank You
22 Replies
wwanalim_intelContributor
Hi,
Greetings and welcome to Intel's forum.
Please give me some time to check on this issue and will get back to you with the update.
Thank you.
Regards,
Fathulnaim
- wwanalim_intel
Hi,
Can I know if the design is from any example design and what is the design to work on?
Michael-CHello
I used a design example from approx 8-10 years ago, which was successful. This new design is similar but I am unsure why. I have attached the cpu_core.qsys file. The pio_cd_sol is the one giving me trouble. I have tried putting it to different address, change type from output to bi-dir, and some other settings, but nothing makes a difference. pio_cmd works perfectly and both appear to be the same.
When the Nios core resets, I think it first it trapped by a watch-dog timer (I was able to trace through it one in the "Debug as Nios" in the Eclipse environment ).
I don't think it is interrupt related as I do not have any interrupts connected in the Nios core for any of the PIO.
Michael
- wwanalim_intel
Hi,
For me to open the file, can I know what version of Quartus you using?
- Michael-C
Quartus Prime
Ver 17.1.0
Build 590 10/25/2017 SJ Edition
Eclipse
Ver Mars.2 Release (4.5.2)
Build: 20160218-0600
- wwanalim_intel
Hi,
Thank you for the reply.
Give me some time to take a look on the design.
- wwanalim_intel
Hi,
It seems the hardware design does not have any issue. We hoping to actually find where the first design come from. I think for now need to check the application code which can the source for the issue.
- Michael-C
I can give you design files, but I want to email them as opposed to posting on this public forum. Is there a way you can connect to my system and see it run live, this might quicken the process.
- wwanalim_intel
Hi,
I will email to you on your registered email and you can send me the design there. Please check your inbox or spam.
- wwanalim_intel
Hi,
Received your design through the email. Allow me some time to take a look on it.
- wwanalim_intel
Hi Michael,
From the email, it seems the problem down to the i/o of the FPGA.
Can we know what the device you are using along with the device number?
Regards,
Fathulnaim
- Michael-C
I am using the Cyclone IV series, specifically the EP4CE40F23C8N.
I changed six of the 22 330ohm resistors to 1.91k ohms. Of those six, two of those outputs started working. That is they remain in a tristate mode. When required, the output goes low able to drive the input to the solid state relay low and enable the output. The other four (of the six), remain tristate. However, when any one of those is set to a low, it causes the FPGA to restart. Of those four, I replaced the solid state relay, incase that one was bad, and it did the same thing.
On a separate note, is there anyway to quickly get to this thread to reply w/o having to search through all of the threads to find this particular one?
- wwanalim_intel
Hi,
I am checking all the pin is correctly used for the SolA and SolB. Can you explain more on SolA and SolB.
- Michael-C
The GPIO SolA and SolB drive banks of solid state relays, PGV612A, to toggle a +24V off board signal to drive solenoids (22 in total).
The anode of the relay is tied to the +5v supply rail. The cathode of the relay is tied to the GPIO through a series resistor. The GPIO toggles between tri-state and logic 0 and is set to LVTTL in the FPGA.
