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Altera_Forum
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13 years ago

NIOS II Locking Up

I am using the 11.1 version of the Eclipse tools. I am having trouble getting through my start up code that takes about 8 seconds. I have 2 points of information.

1) Sometimes it works and sometimes it locks up after changing the code. I have finally determined that I can repeat a line of code

i = 0;

i = 0;

and the code will run again until some other change locks it up. Take one of the lines back out it stops add it back it runs? I spent a while looking at the addresses in the map file and could not determine anything. I seem to have this happen in multiple C++ files.

2) I ran it through the debugger. And it locked up similar to when running from FLASH. So I stepped through the code and it ran. Run it straight again and it locks up. I tried some break points and if the breaks are close to the area that appeared to be locking up it runs (based on debug messages), remove the break points it locks up.

Does anyone have any thoughts on this?

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Here is some related info. I was trying to test the hardware and could not get consistent results pass once fail the next then pass, faile ...

    The gentleman that had developed the FPGA code had some test code. Nothing fancy no interrupts just delays and reading the RAMs to see that the hardware was behaving properly.

    I took his test function and added it to my code. It worked. So I set about trying to break his basic code of loops and delays to be sure it was not a code issue at my end.

    What I found was that if I added a short delay before I checked the hardware I was fine. I medium delay did not read properly, but a long delay worked. According to the FPGA guy a delay should not have mattered.

    Final catch is that I was still not breaking his version of the test code even with the medium delay. I finally removed an unused variable in his function (int i[0x3FFFF]) and broke his code.

    I have a feeling this will be a 'duh' moment. So any idea will be helpful. WHAT WOULD YOU EXAMINE NEXT?

    Thanks for your help!
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I think you definitely have a timing issue with your fpga design.

    Can you recompile/analyze the fpga project or can someone of the fpga team make this for you?

    Otherwise start with a very very simple Nios application, without loading any component driver and try to find out if the problem is with specific operations/addresses
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Cris,

    Thanks for your thoughts.

    We have tried recompiling and the problem still appears to be there. The FPGA designer has done what simulation he can, but much more is constrained by computer limitations. Is there a specific item you can think of to look at?

    I unfortunately did not start to have the problems until the code got large. So I am not sure if I can repeat it with simple code. I had tried to use the debugger, but I had to recompile to avoid our boot loader. I think this may have hidden the problem.

    The next time I see the problem, I am going to try a little harder to repeat it with the debug code since I had not thought of the recompilation issue until later.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I'd concentrate on the timing issue idea.

    What's your system clock frequency? Can you momentarily reduce it and find out if you still have the same problems. Clearly you have to change it in the Quartus fpga project and rebuild all; this may be quite annoying but it should be straighforward and useful to understand the problem.

    Another option is performing a basic TimeQuest analysis and look for negative slacks. With basic I mean using only the minimal clock constraints (see TQ tutorial) without bothering I/Os signals.