Cris,
Thanks for your thoughts.
We have tried recompiling and the problem still appears to be there. The FPGA designer has done what simulation he can, but much more is constrained by computer limitations. Is there a specific item you can think of to look at?
I unfortunately did not start to have the problems until the code got large. So I am not sure if I can repeat it with simple code. I had tried to use the debugger, but I had to recompile to avoid our boot loader. I think this may have hidden the problem.
The next time I see the problem, I am going to try a little harder to repeat it with the debug code since I had not thought of the recompilation issue until later.