Nios II fast pipeline

What do you mean ?

I believe that the 'A' and 'B' fields of all instructions (except call and jmp) cause two 32bit values to be read from the register file during the 'decode' phase (often r0 is read when no value is required).

Either of these can cause a pipeline stall if the required value was written by a non-ALU instruction. Something must forward the result from the ALU to avoid this stall.

dsl,

Thanks a lot for your reply.

I mean, for example, can Nios II fast/standard handle data hazard? Say, to forward a to-be-written register content to an instruction at the decode stage which needs this content to avoid a data hazard.

Hope I clarified my question.

Thanks anyway :)

The 'f' certainly has logic somewhere to allow an instructions to use the result of the previous 2 normal ALU instructions without stalling the pipeline.

Since there aren't enough clock edges to do a write/read pair, some form of data forwarding must be happening.

OTOH the docs don't allow the 's' to stall during the decode phase, possibly that can forward the result of all instructions.

Thanks a lot.

I have found the answer as well. Data forwarding is possible from E/A/W to D.