Honored ContributorHi,
are there any constrains for system clock. I'm interested in lower freq. than default value 50MHz. When I tried lower freq. (1MHz ! ) JTAG UART terminal was not correct. Is Nios II core static design? Thanks Jan
Honored ContributorHi Jan,
That is a good question... I do not have data readily available to answer you but one thing immediately comes to mind: JTAG. If you're using the JTAG UART or debug core, these have a second clock, JTAG Tck, coming in at a frequency that depends on your board/programming cable (max 10MHz or so, I think). I am not familiar with the inner-workings of logic between the JTAG and Avalon/Nios clock domanis, so I cannot speculate further, but you might try 10MHz in the interim to see if this gives you a working system.Honored ContributorThe processor clock must be running at at least 4 times the JTAG clock rate for the JTAG debug core to work correctly. USB-Blaster runs tck at just less than 10MHz so you should ensure your CPU clock is at least 40MHz.
Honored ContributorI tested following configurations
f=5MHz - didn't work f=10MHz - works fine, but JTAG UART was not readable - insted of Hello from Nios output was "Hell frmm Nioos" f=25MHz - OK Core cfg: code from internal RAM, UART 115200 Sw: "Hello from Nios" with output redirected to UART JanHonored ContributorHello Jan / Jesse !
So, about the question "Is Nios II core static design?" Is the answer no ? Forgetting the jtag, would the Nios core continue to work after stop and continue the clock signal or after changing on-the-fly the clock frequency ? FabioHonored ContributorHi pleskacj,
In reply to your question: "are there any constrains for system clock. I'm interested in lower freq. than default value 50MHz." You should get an warning message when you connect the Nios II to a clock that is lower than 20Mhz. Ans yes, this is due to the Jtag clock constraint. Hope that answer you question. SHLHonored Contributorhi all
anyone has the answer to Fabio question? thanks Ale.Honored Contributor
