Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Nios II core minimal frequency?

Hi, are there any constrains for system clock. I'm interested in lower freq. than default value 50MHz. When I tried lower freq. (1MHz ! ) JTAG UART terminal was not correct. Is N...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

hi all

anyone has the answer to Fabio question?

thanks

Ale.

--- Quote End ---

I think the FPGA is static, at least within the range of clock values that I experimented with recently. My Cyclone III NIOS design uses a 100 MHz system clock. I varied the system clock in modest increments between 100MHz and 1MHz to test the power average draw as a function of frequency. My design worked without changes in that range. I didn't test the JTAG UART as my tests were all in standalone mode.

JJS