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Altera_Forum
Honored Contributor
21 years agoNios II core minimal frequency?
Hi, are there any constrains for system clock. I'm interested in lower freq. than default value 50MHz. When I tried lower freq. (1MHz ! ) JTAG UART terminal was not correct. Is N...
Altera_Forum
Honored Contributor
21 years agoHi Jan,
That is a good question... I do not have data readily available to answer you but one thing immediately comes to mind: JTAG. If you're using the JTAG UART or debug core, these have a second clock, JTAG Tck, coming in at a frequency that depends on your board/programming cable (max 10MHz or so, I think). I am not familiar with the inner-workings of logic between the JTAG and Avalon/Nios clock domanis, so I cannot speculate further, but you might try 10MHz in the interim to see if this gives you a working system.