Altera_Forum
Honored Contributor
12 years agoNios II boot Remote Update
I'm working on the Nios II with the device cyclone III, my flash EPCS64 memory
contains 2 FPGA images and 2 softwares. The 1st FPGA image (factory) address is 0, the 1st Nios software address is 0x2614E7, my 2nd FPGA image (application) address is 0x400000 and the 2nd Nios software address is 0x6614E7. When I damage voluntarily my 2nd Nios software I want to come back in my 1st FPGA image. Unfortunately I stay in my 2nd FPGA image but no software runs. The solution would be to enable the watchdog in 1st sof and after to boot on my 2nd FPGA image, and to disable it with my 2nd sof. If there is no 2nd sof present we come back to 1st FPGA image because watchdog wasn't disabled. Unfortunately when I try to read or to write in a Remote update register with my 2nd sof nothing happens I really don't understand maybe have I a problem with my bootloader modified -> From altera wiki (subject EPCS bootloader) http://www.alterawiki.com/wiki/file:asm_bootloader.zip (http://www.alterawiki.com/wiki/file:asm_bootloader.zip) I used the folder to generate my bootloader. I set :# define SOFTWARE_OFFSET 0x6614E7 # define EPCS_FLASH_CONTROLLER_0_BASE 0x08003800 -> defined in my sopc system I do a 'make' I've got my new bootloader.hex I place it my project , update it and then assemble my 2nd FPGA image. I'm in my second FPGA image but no software runs; so I did a 'make CODE_BASE=0', and then it works my second software runs well, but can't read or wirte in RU registers with my application code. Any help would appreciated, last step and my project is finished.