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Altera_Forum's avatar
Altera_Forum
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19 years ago

NIOS II addressing problem

I am having trouble with an SOPC builder component.

I am using signaltap to try to debug it. I have a pointer to an address which I write to and then read from. But the address that is asserted is different in the two cases.

I am using the code below. 

 unsigned short * ptr;
 unsigned short bla;
 int i = 0;
 
 ptr = (unsigned short *)MG1264_INTERFACE_0_BASE+1;
 
 while(1)
 {
  *ptr = (unsigned short)0xaaaa;
  bla = *ptr;
 }

MG1264_INTERFACE_0_BASE is 0x800

as I understand it this should write to address 0x802 and then read from address 0x802. So address bit 1 should be 1 in both read and write.

This is not the case however. Address bit 1 is 1 when I do a write but when I read, address 1 is 0.

Bearing in mind these are the nios address lines and not mine.

Has anyone come across this before or have any idea what the problem may be?

Many thanks,

Richard

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    If you are looking at the address coming from Nios, remember that the databus is 32-bits wide. Assuming your peripheral is 16-bits wide, the Avalon Switch Fabric is taking care of the bus-width matching for you. Therefore, if you really want to see the low order address bits, you'll be better off examining the address at the peripheral.

    BTW, I assume you have no data cache in your system. Otherwise, these accesses will be cached, and the accesses won't make it to your peripheral as anticipated.

    --- Quote Start ---

    originally posted by richy759@Dec 8 2006, 09:30 AM

    this is not the case however. address bit 1 is 1 when i do a write but when i read, address 1 is 0.

    bearing in mind these are the nios address lines and not mine.

    has anyone come across this before or have any idea what the problem may be?

    many thanks,

    richard

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    --- quote end ---

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Thanks for the reply.

    I am looking at both the address coming from the NIOS and going to my peripheral. I have taken into account the bus-matching.

    Also I have no data cache.

    I have set up a simple component which passes through the NIOS cs, data, address lines. I have captured a read cycle in signaltap and can see that a read takes 2 clock cycles and half way through the lsb address latches through.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    I think I have my answer, when reading, the NIOSII seems to always read 32 bits worth and present you with the appropriate 16 bits of data. If you are using the waitrequest line in the interface, you have to be careful when you decide a read cycle has finished or not.

    Richard