Nios doesn't boot using custom bootloader

Be sure that you understand that the EPCS bootloader does not reside in the EPCS flash, itself, but rather in a small onchip (i.e. _on_ FPGA) memory that is a part of the epcs_controller. Any changes you make to the EPCS bootloader must be built into that onchip memory and re-compiled in Quartus II.

If you already understand that portion (it looks like you do), then you're already making sure that this happens and that the instructions you see in that onchip memory match what you'd expect to see in your customer bootloader.

Also, any reason that you're using 11.1sp2? It's a pretty old version is all. You could also replace it with non-assembly code as well. If I recall, there's a single command in the EPCS API that will pretty much do this for you...not sure if it will fit into the 1k bytes that are part of the epcs_controller though. You'd likely have to use another onchip memory....It would be easier to debug/test though.

...I have definitely done this before, so I know it's possible.

Hi Slacker,

Thanks for your answer.

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Be sure that you understand that the EPCS bootloader does not reside in the EPCS flash, itself, but rather in a small onchip (i.e. _on_ FPGA) memory that is a part of the epcs_controller. Any changes you make to the EPCS bootloader must be built into that onchip memory and re-compiled in Quartus II.

If you already understand that portion (it looks like you do), then you're already making sure that this happens and that the instructions you see in that onchip memory match what you'd expect to see in your customer bootloader.

--- Quote End ---

Yes I think I understand well Nios bootloader basics but in detail I am not sure that I am not missing anything.

For example:

- Are the Altera_wiki ASM sources ready to use without modification (except the epcs_controller base address and Nios image offset)?

- I have only mapped the cpu_reset_vector to the ROM containing the hex bootloader. Is there anything else to configure the Hardware?

Maybe I need to debug the Nios boot sequence to see if it can access the epcs.

I have import asm sources as "Custom Makefil for Nios II Software Build Tools Project" but I don't know how to run the debugger with this kind of project.

Do you know how it works?

Have you read how I generate the JIC file? I want to write the nios image at 0x400000 and boot at this address. Did I use the good commands to do it?

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Also, any reason that you're using 11.1sp2? It's a pretty old version is all. You could also replace it with non-assembly code as well. If I recall, there's a single command in the EPCS API that will pretty much do this for you...not sure if it will fit into the 1k bytes that are part of the epcs_controller though. You'd likely have to use another onchip memory....It would be easier to debug/test though.

--- Quote End ---

I use several IP and especially a commercial Transceiver IP developed on an old Quartus version. So I prefer to keep the same Quartus version with a known behavior during development.

I choose the ASM sources because it thought it was more simple as I didn’t need any custom modifications and knew nothing about bootloaders.

I create an 1KB onchip ROM to store the bootloader so I shouldn't be disturb by epcs_rom.

Thanks again.

ps: sorry to reply late, I had to debbug HW problems on other boards...

It works !!!

I had 2 problems:

- I was using an onchip ROM instead of RAM to store the bootloader in SOPC

- Then I have seen after reading back EPCS content that Nios binary file must be written without any byte modification unlike RBF files.

So I have modified the ROM to RAM and the way I write nios file on EPCS and now everything is working.

Now Nios can boot from a custom offset in EPCS and I can update binary file in EPCS !!

Thanks for support.

Hello,

I'm trying to make http://www.alterawiki.com/wiki/epcs_bootloaders assembly example working. I thing I have the same problem as you had : http://www.alteraforum.com/forum/showthread.php?t=41648

In the topic you say: "So I have modified the ROM to RAM and the way I write nios file on EPCS and now everything is working." but you don't tell how you change the way you write the EPCS.

I write the software file in the EPCS the same way as you did, I create a .jic file with my hardware (with RAM and custom boot) and software at the specific address.

PS : Sorry for my bad English.

Thank you.

Flandroid

Hi,

I use 2 methods to write EPCS:

- Quartus jtag flow: generate a jic and use quartus programmer

- Update EPCS content with custom logic to allow product update

The 1st method requires a nios file formated with "intel" format and the second requires "binary" format.

I use this script to generate file:

# echo "Converting SOF file..."

# sof2flash --epcs --compress --input=$sof --output=hw.flash

# echo

echo "Converting ELF file..."

elf2flash --epcs --input=$elf --output=sw.flash

# echo

echo "Creating HEX file..."

# cp hw.flash hw_sw.flash

# chmod 777 hw_sw.flash

# cat sw.flash >> hw_sw.flash

echo "=> Use iHex file to generate JIC with Quartus"

nios2-elf-objcopy --input-target srec --output-target ihex sw.flash $hex_sw --change-addresses=0x400000

echo "=> Use binary file to update epcs nios file (change file extension from .hex to .rbf)"

nios2-elf-objcopy --input-target srec --output-target binary sw.flash $hex_sw_raw1 --change-addresses=0x400000

# nios2-elf-objcopy -I srec -O binary $elf $hex_sw_raw

echo

thank you for your answer but I didn't solved my problem, I still can't boot.

Can you tell me if I am doing something wrong ?

I import the assembly boot project example to eclipse, I change the EPCS address with the one defined in my QSYS, I keep the same software offset as the example one (I changed it in your script) :

# define SOFTWARE_OFFSET 0x1c0000

# define EPCS_FLASH_CONTROLLER_0_BASE 0x04007000

I uncomment the //#define EPCS line.

I changed the build commmand to "make CODE_BASE=0x0;" as describe in the wiki.

Once the boot-loader compiled I get the "my_boot_loader_standalone.hex" that I use as Memory Initialization for On-Chip Memory defined as RAM with 4096 bytes size in Qsys. The avalon bus of the On-Chip Memory is connected to nios (data_master and instruction master). The nios reset memory is the On-Chip Memory address.

I compile the hardware in QSYS and after on quartus. So I get my hw.sof

With quartus programmer I program my fpga hardware and I run my software with eclipse to be sure all is OK.

Then I create the .jic and program the EPCS, I reset the FPGA and nothing append :s.

I can't find a way to debug this problem.

Thank you.

1) you don't need to uncommend# define EPCS because the "#ifdef EPCS / else" are not used.

2)qsys:

check epcs_flash_controller address and lock it to avoid any future modification. it must match EPCS_FLASH_CONTROLLER_0_BASE.

1024 bytes for the ROM is enough.

don't forget to initialize the ROM with "my_boot_loader_standalone.hex". Put this hex file in your project directory and point to it. (in sopc builder I write only "my_boot_loader_standalone" without any path or file extension in the "user created init file" field).

set the processor reset vector to this boot rom.

check the .map file when you generate the jic file. your hex file msut be at the same offset as SOFTWARE_OFFSET.

3) use a simple way to verify your fpga state. for example use logic to toggle an output pin to verify fpga programming and use nios to toggle another pin (or a simple routine as while(1) printf("hello"); with jtag uart) to check nios state.

if nios doesn't boot, try to download the code with eclipse or nios shell (nios2-download -r pj_name.elf) to verify that your hw is working. if it works read again alterawiki 's page, you should have missed something :-)

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1) you don't need to uncommend# define EPCS because the "#ifdef EPCS / else" are not used.

2)qsys:

check epcs_flash_controller address and lock it to avoid any future modification. it must match EPCS_FLASH_CONTROLLER_0_BASE.

1024 bytes for the ROM is enough.

don't forget to initialize the ROM with "my_boot_loader_standalone.hex". Put this hex file in your project directory and point to it. (in sopc builder i write only "my_boot_loader_standalone" without any path or file extension in the "user created init file" field).

set the processor reset vector to this boot rom.

check the .map file when you generate the jic file. your hex file msut be at the same offset as SOFTWARE_OFFSET.

3) use a simple way to verify your fpga state. for example use logic to toggle an output pin to verify fpga programming and use nios to toggle another pin (or a simple routine as while(1) printf("hello"); with jtag uart) to check nios state.

if nios doesn't boot, try to download the code with eclipse or nios shell (nios2-download -r pj_name.elf) to verify that your hw is working. if it works read again alterawiki 's page, you should have missed something :-)

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It works ! Thanks you !!!

I used "select a file" to select my "my_boot_loader_standalone.hex" so I got path and file extension. I tried without any of these like you said and it's work.

Thanks you again.

check epcs_flash_controller address and lock it to avoid any future modification. it must match EPCS_FLASH_CONTROLLER_0_BASE.

1024 bytes for the ROM is enough.

don't forget to initialize the ROM with "my_boot_loader_standalone.hex". Put this hex file in your project directory and point to it. (in sopc builder I write only "my_boot_loader_standalone" without any path or file extension in the "user created init file" field).

set the processor reset vector to this boot rom.

"this boot rom" is 1024 bytes for the ROM that is initialize with "my_boot_loader_standalone.hex"?

"this boot rom" isn't epcs_flash.epcs_control_port? Reset vector isn't EPCS_FLASH_CONTROLLER_0_BASE?

I'm working this,but my system can't boot from EPCS. The Quartus is 13.0,Cyclon v 5CGXFC5C6,my Exception vector memory is DDR3.

Who can tell me this boot rom is what? on chip ram or epcs_flash.epcs_control_port? Reset vector is on chip ram' s address? or EPCS_FLASH_CONTROLLER_0_BASE?

Thank you!