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1) you don't need to uncommend# define EPCS because the "#ifdef EPCS / else" are not used.
2)qsys:
check epcs_flash_controller address and lock it to avoid any future modification. it must match EPCS_FLASH_CONTROLLER_0_BASE.
1024 bytes for the ROM is enough.
don't forget to initialize the ROM with "my_boot_loader_standalone.hex". Put this hex file in your project directory and point to it. (
in sopc builder i write only "my_boot_loader_standalone" without any path or file extension in the "user created init file" field).
set the processor reset vector to this boot rom.
check the .map file when you generate the jic file. your hex file msut be at the same offset as SOFTWARE_OFFSET.
3) use a simple way to verify your fpga state. for example use logic to toggle an output pin to verify fpga programming and use nios to toggle another pin (or a simple routine as while(1) printf("hello"); with jtag uart) to check nios state.
if nios doesn't boot, try to download the code with eclipse or nios shell (nios2-download -r pj_name.elf) to verify that your hw is working. if it works read again alterawiki 's page, you should have missed something :-)
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It works ! Thanks you !!!
I used "select a file" to select my "my_boot_loader_standalone.hex" so I got path and file extension. I tried without any of these like you said and it's work.
Thanks you again.
Honored Contributor
