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Altera_Forum
Honored Contributor
12 years agothank you for your answer but I didn't solved my problem, I still can't boot.
Can you tell me if I am doing something wrong ? I import the assembly boot project example to eclipse, I change the EPCS address with the one defined in my QSYS, I keep the same software offset as the example one (I changed it in your script) : # define SOFTWARE_OFFSET 0x1c0000 # define EPCS_FLASH_CONTROLLER_0_BASE 0x04007000 I uncomment the //#define EPCS line. I changed the build commmand to "make CODE_BASE=0x0;" as describe in the wiki. Once the boot-loader compiled I get the "my_boot_loader_standalone.hex" that I use as Memory Initialization for On-Chip Memory defined as RAM with 4096 bytes size in Qsys. The avalon bus of the On-Chip Memory is connected to nios (data_master and instruction master). The nios reset memory is the On-Chip Memory address. I compile the hardware in QSYS and after on quartus. So I get my hw.sof With quartus programmer I program my fpga hardware and I run my software with eclipse to be sure all is OK. Then I create the .jic and program the EPCS, I reset the FPGA and nothing append :s. I can't find a way to debug this problem. Thank you.