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Altera_Forum's avatar
Altera_Forum
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15 years ago

Multiprocessors and Flash Devices

I am interesting designing a Multiprocessor Nios design with a flash device(or alternative memory device) to store the different codes for each processor. What type of flash devices do people generally use for this type of application ? How does one access this stored code and boot from the flash (or alternative memory) device ?

I know that the SOPC builder has a CFI controller for CFI flashes, but when I looked around at flash devices there seemed to be very few choices of devices with this option. I know there are quite a few new types of storage devices available for storing and booting code (my application doesn't necessitate a flash device, any of the newest, fastest, smallest devices would suffice).

Can anyone can give me some help on this ???

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    In a multiprocessor system you will store each boot image at different memory offsets of the same flash device. For example:

    processor 1 : boot from 0x00000

    processor 2 : boot from 0x20000

    processor 3 : boot from 0x40000

    ....

    These addresses are those you specify when you generate the Nios core, namely the reset address in Nios II properties page.

    AFAIK all parallel flash memories (at least classic NOR devices) have a CFI.

    See for example Am29LV or M29W or S29GL devices.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Or expose the soft reset lines for processors 2 and 3 to some Avalon slave IO, asserting reset when the sopc is reset.

    The code that loads on processor 1 can then copy the code+data for the other processors and then release the soft resets.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    In a multiprocessor system you will store each boot image at different memory offsets of the same flash device. For example:

    processor 1 : boot from 0x00000

    processor 2 : boot from 0x20000

    processor 3 : boot from 0x40000

    ....

    These addresses are those you specify when you generate the Nios core, namely the reset address in Nios II properties page.

    AFAIK all parallel flash memories (at least classic NOR devices) have a CFI.

    See for example Am29LV or M29W or S29GL devices.

    --- Quote End ---

    From your response it sounds like the best choice of non-volotile memory to store my multiprocessor firmware is to use a NOR CFI FLash ?! Is there any "newer" devices that maybe applicable ? If yes what benifits may there be in using them over the standard CFI FLash devices ?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Onething to remember, is that if you are going to write the flash from one of the nios, you'll have to guarantee that the other nios don't to flash cycles at the same time.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Is there any "newer" devices that maybe applicable ? If yes what benifits may there be in using them over the standard CFI FLash devices ?

    --- Quote End ---

    This depend on the capacity and extra features you need.

    For standard usage and up to 1Gbit size you can use Spansion S29GL or similar.

    Take a look to any memory producer website (Spansion, Numonyx, etc) for an overview of flash memories characteristics.