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In a multiprocessor system you will store each boot image at different memory offsets of the same flash device. For example:
processor 1 : boot from 0x00000
processor 2 : boot from 0x20000
processor 3 : boot from 0x40000
....
These addresses are those you specify when you generate the Nios core, namely the reset address in Nios II properties page.
AFAIK all parallel flash memories (at least classic NOR devices) have a CFI.
See for example Am29LV or M29W or S29GL devices.
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From your response it sounds like the best choice of non-volotile memory to store my multiprocessor firmware is to use a NOR CFI FLash ?! Is there any "newer" devices that maybe applicable ? If yes what benifits may there be in using them over the standard CFI FLash devices ?
Honored Contributor
