Altera_Forum
Honored Contributor
20 years agoMissing Memory
Hi:
I've got a Cyclone with NIOS II Quartus 4.1 Attached are 2 SDRAM chips that work great. I nca load the FPGA and then with the IDE load code and step through it. RS232, TImer, PIOs interrupts all up and running. I've then installed a tristate bus with FLASH devices and MISC inuts and outputs with 245 and 573 type gates and latches (All 8 bit). I can't see anything external to the FPGA on this tristate bus. I've shared address and data for that tristate bus. But kept Chip Selects, Read, Write and output enables seperate. What did I forget??? George