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Altera_Forum
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14 years ago

memory transfer rate on a EP4CE75F23CN with MT47H16M16BG-5E

Good morning,

I have a data rate problem with DDR2.

I had to developp an electronical board for image processing in real time.

I used the 3c120 development kit as prototype wich contain a EP3C120F780C7 with MT47H32M16CC-3, then we developed our own board based on a EP4CE75F23CN with a MT47H16M16BG-5E.

The design SOPC is exactly the same :

DDR2 SDRAM controller with ALTMEMPHY @ 167MHz, full mode, 16DQ

NIOSII @ 125MHz

The problem is when I test the data rate transfer on the DDR2 I get a very bad rate on the Cyclone IV :

10.05 Mo/s on the DEV KIT EP3C120

3.74 Mo/s on my board.

To sum up :

EP3C120F780C7

+ MT47H32M16CC-3

= 10.05Mo/s

EP4CE75F23CN

+ MT47H16M16BG-5E

= 3.74Mo/s

I need 10.05 Mo/s on my board. Do you have an idea ?

Thank you in advance.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    With a simple program running on the nios. It create files which contain 100ko of 0. Those file are rewritted in a loop.

    I know that those figures are not correct, however the result should be the same on the two boards.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Do you think that MT47H16M16BG-5E (that I use) is 3 times slower than MT47H32M16CC-3 (that DK-3C120 use) ?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Well. i was thinking about the way you use it. Software writes to the memory don't lead to the fastest transfer rates. Also beware of the burstsize that you use.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I don't use burst on the NIOS II, neither on the Clock crossing bridge (which is between the NIOS and the DDR2 SDRAM controller).

    However I can see "Memory Burst Length = 4" In the parameter of the MT47H16M16BG-5E in sopc builder.

    I attach the DDR2 parameter that I entered.

    To create this preset, I took the "Micron MT47H16M16BG-37E" preset which is include in the list preset as default and I change the "CAS Latency" from 4 to 3".

    Did I make mistake ?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    Efficiency is determined by how you access the DDR memory. These types of memory are only efficient when you access them with burst transfers.

    Therefore it is wise to allow bursttransfers with the bridge.

    It will not be the memory being the bottleneck but the way how you access this memory.

    regards
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    To sum up, In order to improve the transfer rate, I have to allow burst on the

    - NIOS IP

    - Clock crossing bridge

    Do I need to modify something on the uClinux make menuconfig or in the config.c ?

    Do you think the different will be important ?

    In the past I already try to make burst transfer under uClinux but I never succeed...

    Thank in advance.