Altera_Forum
Honored Contributor
21 years agoLots of warnings during VHDL compilation
Hi,
as I am compiling a simple design, containing a Nios-II processor, the Quartus-II VHDL compiler spews quite some warning messages. A snippet: info: running quartus ii analysis & synthesisinfo: version 4.2 build 156 11/29/2004 sj web edition
info: processing started: sun feb 06 18:52:56 2005
info: command: quartus_map --import_settings_files=on --export_settings_files=off first_nios -c first_nios
... lines ommitted for clarity ...
warning: vhdl process statement warning at cpu_jtag_debug_module.vhd(236): signal "usr1" is read inside the process statement but isn't in the process statement's sensivitity list
warning: vhdl process statement warning at cpu_jtag_debug_module.vhd(236): signal "ena" is read inside the process statement but isn't in the process statement's sensivitity list
warning: vhdl process statement warning at cpu_jtag_debug_module.vhd(239): signal "usr1" is read inside the process statement but isn't in the process statement's sensivitity list
..
info: power-up level of register "rollator:inst|reset_clk_domain_synch_module:reset_clk_domain_synch|data_in_d1" is not specified -- using power-up level of high to minimize register
warning: reduced register "rollator:inst|reset_clk_domain_synch_module:reset_clk_domain_synch|data_in_d1" with stuck data_in port to stuck value vcc
... ..And a lot more warnings having to do with signals being stuck at either VCC or GND. Now my question is: is it normal for a Nios-II design to generate a lot of VHDL compilation warnings ? Or am I making a mistake here (certainly would not rule this out) ? What are your experiences ? Bye, Roland.