'Launching a Hello World Nios II Hardware configuration' has encountered a problem.

--- Quote Start ---

Hi all,

After successful building of sample hello world project, self has chosen 'Run As' and 'Nios II Hardware' options to check the execution as per the steps written in instruction manual for beginners. But, the launching has failed with the following message.

'launching a hello_world_0 nios ii hardware configuration' has encountered a problem. downloading elf process failed.

Please find the attachment for more details and I request someone to help in resolving the issue.

Nios II Software Build Tools for Eclipse version: 13.0

Development Board: De0-Nano

Thanks in advance

--- Quote End ---

Update from previous post:

There are a lot of steps you need to execute before you can sucessfully download the program to the board.

- Qsys configuration correct & compiled correctly ?

- Verilog connections betweek QSYS generated modal and board hardware are correct (clock etc) ?

- Download of compiled code do board.

- Generate correct model in Eclipse (or regenerate BSP)

- Compile bsp project.

- Compile main project.

- Download project to processor => normally, if you did all things as they should, it should work.

What i did to check if verilog instantiation of model was running, i let a LED blink from som additional verilog code in the project so i could see that the model was downloaded and running. Anyway, you also better look at what the post below says.

What i sometimes see is that right clicking on the project itself and then going to run as / debug as works fine while starting it form the main tool bar does not, (i thought i selected the right project before pressing te button) I also had the problem sometimes when i had deleted a previous configuration, or when starting the first time because the wrong or multiple elf files were selected.

Best Regards,

Johi.

First, make sure you've used the Quartus programmer to download the FPGA configuration sof file.

Note that the run as nios ii hardware command uses the most recently used run configuration. Make sure you click on the application, not the BSP when you attempt to run. Also, you should check your target configuration. To do this, select Run Configurations... from the Run menu. Unless you've changed it the configuration name should match your project name + Hardware configuration. Click the Target Connection tab. Normally, there is only one entry in the processors field. Click it. Then click Refresh Connections. This will ensure that the software tools have a good JTAG connection.

I usually uncheck "Ignore mismatched system ID" and "Ignore mismatched system timestamp" These checks verify that your software is compiled for the FPGA configuration that is actually loaded on the board. It's frustrating to look for a bug that turns out to be due to mismatch between hardware and software.

Under Download, check all the boxes unless you know you have a reason not to. Finally, click apply and run. The next time you want to run, click the round green play button on the toolbar.

Hi Johi & Galfonz

Thanks a lot for your speedy response :)

Btw, I've re-checked the steps involved in generating Qsys configuration and made the following observations.

Step#1: Created a new Qsys system with necessary settings.

Step#2: Generated the configuration with 0 errors and 0 warnings.

Step#3: However, upon successful generation, the verilog HDL file (.v file) generated from the synthesis hasn't got updated on its own as per the inputs (clock & reset) and output (led port details) settings made in 'Qsys' earlier in Step#1. (highlighted the same in the attachment)

Please see the attachments for more details..

As the compilation is getting failed because of Step#3, self has manually changed the inputs and outputs in qsys.v file (which was originally generated on synthesis) to complete Full Compilation process with no errors. Kindly correct me, if my approach is something wrong here in this!

Thanks in advance.

Hello Babloo,

Are you sure you added the .QIP file, generated by qsys to your project ?

You can do this under assingment / settings / files, there shoud be a .QIP file added to the project. As far as I know, this file is used as a kind of reference so Quartus can find the file generated by Qsys. If you do forget this step, the Qsys device will not compile ?

If you are not sure that qsys updated the .v files in the automatically generated code, delete it, generate again from qsys, they should re-appear.

Best regards,

Jogi

The first error is probably caused because you have included both the .qsys and .qip files in your quartus project. Use one or the other. If you use the .qsys file, the code for the qsys project is regenerated every time you compile your project in quartus. It is recommended when you are updating the qsys project often. If you use the .qip file, you need to remember to regenerate in qsys when needed, but your compilation doesn't spend the extra time generating qsys.

The second error is probably caused because the instatiation of the qsys generated module in your .v file doesn't match the component created by qsys. Note that if you have nothing else, you can just make the qip or qsys file the top level in the project and forget about the .v file entirely.

who can help me about the problem below ?

**** Build of configuration Default for project mynios_ch395 ****

make all

系统找不到指定的路径。

系统找不到指定的路径。

Info: Building ../mynios_ch395_bsp/

make --no-print-directory -C ../mynios_ch395_bsp/

cygpath: can't convert empty path

process_begin: CreateProcess(NULL, pwd, ...) failed.

make[1]: *** No rule to make target `/system.h', needed by `all'. Stop.

make: *** [../mynios_ch395_bsp/-recurs-make-lib] Error 2

**** Build Finished ****