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Altera_Forum
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10 years ago

'Launching a Hello World Nios II Hardware configuration' has encountered a problem.

Hi all, After successful building of sample hello world project, self has chosen 'Run As' and 'Nios II Hardware' options to check the execution as per the steps written in instruction manual for b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Johi & Galfonz

Thanks a lot for your speedy response :)

Btw, I've re-checked the steps involved in generating Qsys configuration and made the following observations.

Step#1: Created a new Qsys system with necessary settings.

Step#2: Generated the configuration with 0 errors and 0 warnings.

Step#3: However, upon successful generation, the verilog HDL file (.v file) generated from the synthesis hasn't got updated on its own as per the inputs (clock & reset) and output (led port details) settings made in 'Qsys' earlier in Step#1. (highlighted the same in the attachment)

Please see the attachments for more details..

As the compilation is getting failed because of Step#3, self has manually changed the inputs and outputs in qsys.v file (which was originally generated on synthesis) to complete Full Compilation process with no errors. Kindly correct me, if my approach is something wrong here in this!

Thanks in advance.