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originally posted by weizbox@Aug 26 2005, 02:34 PM
for the application that im going to be using it for, it would have it be counting pulse width, height, and frequency, so i wouldnt need to be sending a stream of this data over the ethernet, just a numbers after it has been sorted out on the fpga side. --- Quote End ---
Wow. I hope you're not trying to do the pulse width/frequency/etc. stuff in software, because that's way more than Linux (or even a no-OS app) could handle.
That said, this is where Nios shines: the ease of creating custom peripherals. You're going to have to look at your algorithm and split it into "fast tasks" (which need to keep up with the sample rate) and "slow tasks" (which don't). Edge detection/windowing/filtering are examples of fast tasks, and sending packets on Ethernet is a slow task.
Fast tasks will need to be done in hardware on the FPGA, then their results will be passed on to the Nios system (via an Avalon bus interface) where the slow stuff will get done.
If you need to do any signal processing, it looks like you're going to want to use a Stratix II. You might want to look at Altera's DSP Builder evaluation package (which also supports Nios II). I think it's what you're looking for, or at least in the ballpark.
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originally posted by weizbox@Aug 26 2005, 02:34 PM
thanks for clearing up the fpga / linux stuff, but i still feel lost on how its all setup on this board and whats runnning and where, etc. but ill check into it a bit more later on, certainly have enough docs on it. --- Quote End ---
Let me see if I can help clear this up...
It's like the network stack; it's a layer cake.
The bottom layer is the physical hardware. Altera FPGA, ADC, Flash, RAM, etc. live here.
Firmware is designed in Verilog or VHDL. Things like state machines, combinational and registered logic, etc. This gets turned into a bit pattern that is used to configure the FPGA so it acts like the custom firmware says.
One day, someone realized that there were so many gates/registers/RAM bits available in FPGAs that you could design a CPU entirely in firmware. As far as the FPGA is concerned, it's a lot of flip flops and gates, but to us humans, it's a CPU.
Once you have a CPU and hook up memory to it, you have a computer. You can write programs for this and run them just like any other PC, albeit with entirely different capabilities.
This leads to confusion since there are now two different types of "stored programs"; the FPGA configuration bit pattern, and the CPU's stored program. I refer to the former as "firmware" and the latter as "software", but this is far from a universal standard. Be careful.
Once you have CPUs that can run programs, you can write programs that are operating systems, upon which other programs may be run. The cake is getting rather tall, isn't it?
So now we have a system where you can have custom hardware as well as software. It's very flexible, yet more work since there is more design effort on the part of the end user. Enter SOPC Builder, which simplifies a lot of this by taking care of the bus architecture, address decoding, timing, interrupts, multiple bus masters, etc. for you, and brings the workload down to a more sane level.
The ultimate price for this flwxibility is in speed and power consumption. On a Cyclone, you should expect to get a CPU clock speed between 50-100 MHz. (You'll have to be really careful to get 100 MHz.) On a Stratix, I think you can add about 50 MHz to that. Compare to modern DSPs that generally run in the 200 MHz to 1.0 GHz range. Regarding power consumption, the Nios II has no sleep modes nor any way to enable/disable the clock tree to parts of the circuit, so you'll be running "full power" at all times.
Hope this clears some of it up...?
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