jtag_uart isn't simulated by ModelSim.

Hi Shev,

Gerally it´s not a problem to use an internal pll. You just have to take care on constraining of your Pins and on the phase-shift for the external clock!

Hi, JacoL

Do you think, that pll is a root of problems? Why?

Hi again,

what I meant is just concerning the SDRAM. If you generate the Clock for the SDRAM in the FPGA via the PLL you have to create two clocks. The internal Clock for the CPU and the SDRAM controller is 100MHz for example. The clock two the SDRAm is 100MHz, too but has a phaseshift to compensate the runtime in the FPGA (at 100MHz roundabout -1ns to -2ns). You can get the right shift from the TimeQuest analyzer.

I would try something different with JTAG. Try to decouple the JTAG UART from the clock-crossing bridge and couple it directly to the cpu. Let it run with pll_c0 Clock. Maybe this helps you out.

I tried to connect directly jtag_uart to cpu without a clock-crossing bridge. But it didn't work either.

I have a very strange situation - design created for Cyclone III device family in SOPC Builder isn't simulated, but fo Cyclone II is simulated. Why? I don't know. Differences between their structure of design - ddr controller.

Now I'm working with the new Quartus project for Cyclone II. Its design is the same like a previous Cyclone III design. It's simulated and jtag_uart works. But I got a new problem - addressing inside my system.

I.e. I use cpu, ddr controller, jtag_uart and my component. I create by pll 3 clocks (pll0 - 50Mhz, pll1 - 100Mhz, pll2 - 60Mhz). Cpu uses pll0, jtag_uart and my componet use pll2. There are clock-crossing briges between cpu - ddr controller (ddr_ccb), cpu - jtag_uart and my component (peripheral_ccb) and my_component - ddr_ccb. DDR controller uses the pll0.

I use this tangled logic, because the same in preevious Cyclone III design.

I generate with SOPC Bulder files for simuation and run in ModelSim the test program (use Nios II Software Builder Tools). This program executes 'malloc', which returns an address. I place data to this address and transmit this address to my component. Than my component tries to read data at this address. But readdata = 32'x. Why? I don't know. May be My component should transform the address. But how should it do?

Hi again,

maybe a screen of this actual sopc builder would be helpfull. Can you post it?

I've solved this problem. I chose Skip Calibration (it's approximatly 30ms of the simulation) and used reduced drivers and Small C library. And I got an answer from jtag_uart.

Long time of the startup code was a root of this problem.