jtag_uart isn't simulated by ModelSim.

I tried to connect directly jtag_uart to cpu without a clock-crossing bridge. But it didn't work either.

I have a very strange situation - design created for Cyclone III device family in SOPC Builder isn't simulated, but fo Cyclone II is simulated. Why? I don't know. Differences between their structure of design - ddr controller.

Now I'm working with the new Quartus project for Cyclone II. Its design is the same like a previous Cyclone III design. It's simulated and jtag_uart works. But I got a new problem - addressing inside my system.

I.e. I use cpu, ddr controller, jtag_uart and my component. I create by pll 3 clocks (pll0 - 50Mhz, pll1 - 100Mhz, pll2 - 60Mhz). Cpu uses pll0, jtag_uart and my componet use pll2. There are clock-crossing briges between cpu - ddr controller (ddr_ccb), cpu - jtag_uart and my component (peripheral_ccb) and my_component - ddr_ccb. DDR controller uses the pll0.

I use this tangled logic, because the same in preevious Cyclone III design.

I generate with SOPC Bulder files for simuation and run in ModelSim the test program (use Nios II Software Builder Tools). This program executes 'malloc', which returns an address. I place data to this address and transmit this address to my component. Than my component tries to read data at this address. But readdata = 32'x. Why? I don't know. May be My component should transform the address. But how should it do?