jtag_uart isn't simulated by ModelSim.

Hi again,

what I meant is just concerning the SDRAM. If you generate the Clock for the SDRAM in the FPGA via the PLL you have to create two clocks. The internal Clock for the CPU and the SDRAM controller is 100MHz for example. The clock two the SDRAm is 100MHz, too but has a phaseshift to compensate the runtime in the FPGA (at 100MHz roundabout -1ns to -2ns). You can get the right shift from the TimeQuest analyzer.

I would try something different with JTAG. Try to decouple the JTAG UART from the clock-crossing bridge and couple it directly to the cpu. Let it run with pll_c0 Clock. Maybe this helps you out.