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Altera_Forum's avatar
Altera_Forum
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16 years ago

Issue using SGDMA to frame buffer

Hi,

I am buffering frames using an SGDMA. I was wondering if anyone has come across the following problem:

After transferring successfully to the ddr2 with several descriptors, the ready signal from the SGDMA drops for good, thereby stalling the frame transfer.

But when using a much smaller frame, say, 100 x 64 pixels instead of 800 x 480, the stalling problem never happens.

Things I have ruled out:

-All timing has been met.

-The descriptors were setup successfully.

-The DDR2 memory passes a read and write test for the entire address range.

Thanks!

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  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi BadOmen,

    If I have multiple AV-ST video streams that I want to write to memory (each has its own frame memory space), do I instante multiple copies of the mSGDMA (ie. one per AV-ST video stream) or is there a way to cut down on the resources? Any suggestions would be appreciated!

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Since it's a single channel DMA the easiest way would be to have multiple DMAs assuming all the video feeds are concurrent. If you only need to write one video frame at a time to memory then a single DMA should be sufficient along with a streaming mux that selects the appropriate input.

    If the video streams are concurrent and you wanted to use a single DMA then you would need to break each frame down into smaller transfers and constantly feed descriptors into the DMA cycling through each video input a portion of a frame at a time. Of course you'll need a large enough buffer for each video input to hold the incoming data while other video inputs are being written out to memory.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi BadOmen,

    I understand that the mSGDMA was designed to work with one clock domain. For the case where I want to write AV-ST data to AV-MM location, assume the AV-ST is running at CLK1 speed while AV-MM (memory interface) running at a different CLK2 speed. If I want to have a different clocks for the two interfaces, what is the best approach?

    - Add a AV-ST dual-clock FIFO before the mSGDMA block to convert the AV-ST to the AV-MM clock domain and then run the mSGDMA with AV-MM clock domain; OR

    - Change the SCFIFO instantiated inside the "write master" block of mSGDMA to a DCFIFO; OR

    - Another approach???

    Appreciate your feedback!
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The first approach would be best even though it increases the latency through the DMA and uses more memory resources. I looked into using DCFIFO a while back but that will change the latency of the FIFO used, full, and empty signals which drives some of the control logic that the DMA uses to backpressure on the MM side. So it's doable to make that change but it would take some work to redo the skid logic inside and there is also some information like sop/eop/empty from the ST port that would need to cross clock domains as well which would need to be taken care of as well. If you select a shallow FIFO and target a device with MLABs then you'll probably get a clock crossing FIFO that doesn't use memory blocks.