Issue using SGDMA to frame buffer

The first approach would be best even though it increases the latency through the DMA and uses more memory resources. I looked into using DCFIFO a while back but that will change the latency of the FIFO used, full, and empty signals which drives some of the control logic that the DMA uses to backpressure on the MM side. So it's doable to make that change but it would take some work to redo the skid logic inside and there is also some information like sop/eop/empty from the ST port that would need to cross clock domains as well which would need to be taken care of as well. If you select a shallow FIFO and target a device with MLABs then you'll probably get a clock crossing FIFO that doesn't use memory blocks.