Forum Discussion
Altera_Forum
Honored Contributor
10 years agoHi BadOmen,
I understand that the mSGDMA was designed to work with one clock domain. For the case where I want to write AV-ST data to AV-MM location, assume the AV-ST is running at CLK1 speed while AV-MM (memory interface) running at a different CLK2 speed. If I want to have a different clocks for the two interfaces, what is the best approach? - Add a AV-ST dual-clock FIFO before the mSGDMA block to convert the AV-ST to the AV-MM clock domain and then run the mSGDMA with AV-MM clock domain; OR - Change the SCFIFO instantiated inside the "write master" block of mSGDMA to a DCFIFO; OR - Another approach??? Appreciate your feedback!