Honored ContributorHi,
I'm wondering if can I change clocking frequency of Nios2 processor from 0 to fmax [MHz]. It's usefull for static debugging of my soft and hardware. I also need JTAG debugger to be working during no clock signal connected to processor. Best Regards, Mariusz
Honored ContributorNope. You've got to have ~25MHz just to satisfy JTAG requirements.
- slackerHonored ContributorHi,
what is this static debugging. can you please explain clearly? thanks in advance prasadHonored Contributor"Static debugging" - I mean that I can stop clock signal connected to processor to examine it's outputs, or apply some clock ticks manually , and then switch clock to normal speed - all this without loosing debug connection.
Honored ContributorIt kind of depends on the peripherals. The Nios2 core itself, and the Altera logic, can go down to DC. But several peripherals can't go down to DC. Some examples I can think of:[list][*]Any JTAG peripheral (see above re: 25 MHz clock minimum, also some things like Nios2 flash programmer need at least a 50 MHz clock)
[*] SDRAM (stop clock and it won't get refreshed) [*] Ethernet (usually has its own clock, though) [/list]The Nios2 IDE debugger doesn't stop the clock, and probably won't like it if you do, however it has its own way of stopping the processor.Honored ContributorI've system with 2 clock domains: fast (33MHz) , and slow (~100kHz). Special module switch this clocks - when chipselect to one of slaves is selected,or write_n or read_n frmo one master is asserted, slow clock is connected, otherwise system is clocked by fast clock.
When master make short transfer (duration ~20 slow clock cycles) everything is OK, but during longer operations debuger stop working, and show message that watchdog timer has expired. In my system i haven't any timer. I use JTAG debug module inside Nios2 cpu. Probably this watchdog is inside debuger at PC side. Does anybody know if i can change overflow period of this watchdog, or switch his off?Honored Contributor--- quote start ---
in my system i haven't any timer. i use jtag debug module inside nios2 cpu. probably this watchdog is inside debuger at pc side.[/b]
--- quote end ---
or the watchdog is using the jtag clock, which comes from your usb blaster, and i think it's always 10 mhz.
<!--quotebegin-krzymar@Oct 6 2005, 04:37 AM does anybody know if i can change overflow period of this watchdog, or switch his off? --- Quote End --- I've never heard of it, but if someone does, please post it here so we'll have it for future reference.
