Honored Contributor
Honored ContributorI've system with 2 clock domains: fast (33MHz) , and slow (~100kHz). Special module switch this clocks - when chipselect to one of slaves is selected,or write_n or read_n frmo one master is asserted, slow clock is connected, otherwise system is clocked by fast clock.
When master make short transfer (duration ~20 slow clock cycles) everything is OK, but during longer operations debuger stop working, and show message that watchdog timer has expired. In my system i haven't any timer. I use JTAG debug module inside Nios2 cpu. Probably this watchdog is inside debuger at PC side. Does anybody know if i can change overflow period of this watchdog, or switch his off?
