Forum Discussion
Honored ContributorInterfacing to a daughter card through PROTO"
Hi. I need to connect to a self-made daughtercard through the proto2 connector on a Nios Development Kit, Cyclone Edition. All the I/O are on the J16 connector. Do I need to enable something special to make it work? Are any of the I/Os on proto2 connected to something else on the development kit? For example: I see the same signal on Y8 on the J16 as on L9 on the J11.
And L9 on J11 is actually H17 if I understood the documentation right. In mnl_nios2_board_cyclone_1c20.pdf pin 35 in J11 is called L9. But if you look through nios_1c20_board_schematic.pdf you'll find that L9 is connected to 1.5 V and that pin 35 is actually H17 which is the same as A00 to the Compact Flash connector. So the documentation is pretty bad. Another example is that in nios_1c20_board_schematic.pdf the signals that go through the buffers is call proto1_IOXX and proto2_IOXX from the FPGA, and at the buffers both are called proto_IOXX and proto5_IOXX after the buffers. This make reading through the documentation pretty bad. But, to my original question again. Are the I/O on proto2 connected to anything else on the board? Ole11 Replies
Altera_ForumHi, I'm trying to use PROTO2 too.
I' m experiencing some problems. I guess that the reference manual has some errors, at least in the PROTO2 interface pin descritpion. It is assumed to have 41 IO pins but I counted 42 trough J16 and J15( 30 on J16 and 12 on j15). Am I wrong? Where? It could mean that some connections are replicated, It could explain a serie of strange behaviours using a 16 Bit Out PIO connected to J16. Can we work togheter to achieve a common understanding?! Bye!!- Altera_Forum
I'm using an evaluation board based on cyclone EP1c20. Actually I' m using 16 pin on J16 (40 pinPROTO2 connector) for an OUTPUT PIO 16 bit wide.
From the reference manual seems that all the FPGA pins (except RESET_n) connected to j16 are general purpose, Isn't it? If yes let me go ahead..... I wanted to debug the system, so I slightly modified the "hello led" example adding a stupid loop in this way: "....... alt_u16 i; i=0; while(i<10){ IOWR_ALTERA_AVALON_PIO_DATA(OUT_PIO_BASE, 0); IOWR_ALTERA_AVALON_PIO_DATA(OUT_PIO_BASE, 0xa); IOWR_ALTERA_AVALON_PIO_DATA(OUT_PIO_BASE, 0xaa); IOWR_ALTERA_AVALON_PIO_DATA(OUT_PIO_BASE, 0xaaa); IOWR_ALTERA_AVALON_PIO_DATA(OUT_PIO_BASE, 0xaaaa); i++; } .......", what i see is the right sequence on OUT_PIO[0..15] up to the prefinal assignment but, on the last I see 0x8aaaa instead of 0xaaaa. It's not all. If I do this serie of assignments out of the loop, everithing works fine. Actually It works fine even if I do the assigments in a reversed order within the loop........ http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif Has someone an idea to suggest me?? Thanks - Altera_Forum
Attention: Nios 1.1 Kit contains old version 1.1 with wrong Pin description
check latest Cyclone "Nios Development Board Reference Manual, Cyclone Edition" (ver 1.2, Jan 2005, 2,834 KB) MNL-N2DEVLBDCYC-1.2 Table 1–1. Reference Manual Revision History Date Description December 2004 Corrected PROTO1 pinout information listed in Figures 1-5, 1-6, and 1-7. These figures were incorrect in the September 2004 version of this document (MNL-N2DEVLBDCYC-1.1). The document part number is found on page ii. September 2004 Updates for Nios II 1.01 release. May 2004 Updated Appendix B: Restore the Factory Configuration. January 2004 Pin table corrections. July 2003 Reflects new directory structure for SOPC Builder 3.0 and Nios Development Kit version 3.1. May 2003 Minor revisions and edits. March 2003 First publication of a reference manual. This manual is Cyclone-device specific. - Altera_Forum
Thanks!
I was referring to MNL-NIOCYCBD-1.3 but I didn't find differences with MNL-N2DEVLBDCYC-1.0 about pin description of PROTO2 interface.... - Altera_Forum
I see that PROTO2 is supposed to have 41 IO general purpose pins, but from fig 8 (pag.22) seems that are 42 IO pins. I've just find that pin 38 on J16 is used for CARD_SELn signal and so it isn't general purpose like the label U8 could suggest.
Bye!! - Altera_Forum
I found out a couple of things today. First: the IO called Y8, pin 33 on J16 seems to be connected to H17, pin 35 on J11. Don't ask me how or why, but I get the same signal on both these pins. Second: IO T13, pin 21 on J16 is connected via a pulldown. This shouldn't have any effect I thought, but it actually distorts the signal a little. A square signal get a little slope on the right flank for me on this pin. IO T12, pin 27 on J16 is connected to both a pullup and a pulldown. Again, this shouldn't have any effect when a signal i applied, but even without a signal there, I get some really weird and periodic noise/signal on that pin. I also have some issues with IO W12. It almost looked like the discharge slope of a capacitor. I have no idea what might cause this.
Ole - Altera_Forum
Hi! Some pins on j16 and j12 Interface are shared between PROTO1 and compact flash connector
take a look at page 15 of the MNL_NIOSCYCBD-1.3 - Altera_Forum
Do you have a link to MNL_NIOSCYCBD-1.3? I can't seem to find it on neither Google nor Alteras search.
Ole - Altera_Forum
- Altera_Forum
Some confusion ?
this link ist to MNL-NIOSCYCBD-1.3, that's NIOS and not NIOSII (from JANUARY 2004) I think the board is still the same (for NIOS and NIOSII), the latest actual document is "Nios Development Board Reference Manual, Cyclone Edition" (ver 1.2, Jan 2005, 2,834 KB) MNL-N2DEVLBDCYC-1.2 ???
