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Altera_Forum's avatar
Altera_Forum
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20 years ago

Incompatibilities with avalon sdram controller

my design consists of NIOS II (v5 SP1) with external SRAM, SDRAM and several peripherals, all connected through a single avalon tri state bus. During development a Micron 128 MBit (8MB x 16) SDRAM (MT48LC8M16A2) was used without any problem. Now at production line a ISSI device (IS42S16800A) is used, which constantly causes R/W verification errors. Modifying the phase shift of its clock didn't solve the problem.

- Has anybody made similar experiences with different SDRAMs at the 'Avalon SDRAM Controller' ?

- Any suggestions ?

Mike

Added later:

After further tests I discovered that the ISSI device with index 'B' has no problems.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    hi~

    I have also experienced that problem.

    But, there was no solution as i know

    There was some difference with Nios II 5.0 Eval. Edition and Normal Edition(?)

    Eval. Edition was weaker(?) for SDRAM

    I was trying to modifying Phase shift, from -43 to -83 for -1 step.

    As i have modified my design, i should have modified phase shift value.

    how many trying?

    my suggestion is using LogicLock Region for SDRAM Controller.

    you find it, "Assignments" Menu in Quartus II
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Meanwhile I've tested different 128Mbit-devices (8MB x 16) all with 50MHz Clock and a clock phase shift of -3ns to -6ns: 

    ISSI          IS42S16800A-7TL        <FAILED>
ISSI          IS42S16800B-7TL        <OK>
AMIC         A43L3616V-7              <OK>
MICRON    MT48LC8M16A2-8BE    <OK>
SAMSUNG  K4S281632F-UC75      <OK>