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Altera_Forum
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20 years ago

Incompatibilities with avalon sdram controller

my design consists of NIOS II (v5 SP1) with external SRAM, SDRAM and several peripherals, all connected through a single avalon tri state bus. During development a Micron 128 MBit (8MB x 16) SDRAM (M...
Altera_Forum's avatar
Altera_Forum
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20 years ago

Meanwhile I've tested different 128Mbit-devices (8MB x 16) all with 50MHz Clock and a clock phase shift of -3ns to -6ns: 

ISSI          IS42S16800A-7TL        <FAILED>
ISSI          IS42S16800B-7TL        <OK>
AMIC         A43L3616V-7              <OK>
MICRON    MT48LC8M16A2-8BE    <OK>
SAMSUNG  K4S281632F-UC75      <OK>