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Altera_Forum
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20 years ago

Incompatibilities with avalon sdram controller

my design consists of NIOS II (v5 SP1) with external SRAM, SDRAM and several peripherals, all connected through a single avalon tri state bus. During development a Micron 128 MBit (8MB x 16) SDRAM (M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

hi~

I have also experienced that problem.

But, there was no solution as i know

There was some difference with Nios II 5.0 Eval. Edition and Normal Edition(?)

Eval. Edition was weaker(?) for SDRAM

I was trying to modifying Phase shift, from -43 to -83 for -1 step.

As i have modified my design, i should have modified phase shift value.

how many trying?

my suggestion is using LogicLock Region for SDRAM Controller.

you find it, "Assignments" Menu in Quartus II