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Altera_Forum's avatar
Altera_Forum
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21 years ago

Image Select Capability?

We want to implement "Image Select Capability" from Flash in "CPLD Config contrller " of custom Nios board.

We have learnt the idea from P16 of AN346.pdf -- Using the Nios Development Board Configuration Controller Reference Designs. And we'd like to use VHDL to implement not AHDL in original one, which does't implement the "Image Select Capability". Here comes some problems:

1. Can the design fit the EPM7128(EPM3128)?

2. Where to store the "Marker" of which image to load? And then how to read the "Marker" to CPLD?

3. Eeee.., can Altera have such a design for us to have a reference? Haha... lazybones

4. BTW, on the same AN346.pdf , P9, Figure 4. Configuration Controller Boot Sequence Flowchart for Cyclone

Devices: How to implement the "Load user image from serial configuration device to Cyclone device

" , as we know the DATA0 and DCLK are used both in the AS and PS mode? Does CPLD just "idle"(High Z) in this state for EPCS and FPGA config in AS mode?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    for 4 : The original CPLD config controller is writted by AHDL,and I don't know much about the AHDL.

    More Questions:

    5. JTAG pins: should all 4 pins:TDI,TDO,TMS,TCK be pulled-up or pull down 10 kohm resistor? Cause I find Twister board's solution is YES while Altera Nios cyclone board is No ( TDO isn't pulled anything)

    6. PS pins: nSTATUS and nCONF_DONE are IO pins in FPGA. But we find they just are outports in PS mode from FPGA. Could we just design them as inports in CPLD side?
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    1: yes. our current cyclone board has a custom loader CPLD design

    that supports multiple images. the loader part fits into a EPM3128.

    2: In the flash where you load the image from.

    You could also use the UFM of a MAX II (non ES device assumed)

    4: Didn't delve into AN346, but if you want to support AS from an EPCS

    as well, the loader CPLD has to tristate all config outputs to the FPGA,

    or else they would contend.

    5: This is covered in the datasheet. TDO,TMS up / TCK down / TDO open

    6. Yes

    Cheers, Roger
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    (2). UFM V.S. external Flash device

    We want to store "MARKER" in the external Flash device , too. The only thing we worried about is Flash will go to "dead" if writtened by the same address so many times. However maybe it will never happen during the life of the product, haha.... Such problem will UFM face, I think.
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    FLASH endurance is a function of erase/program cycles. what you can do is to dedicate an entire or sector

    (or part of it) to store your markers, last entry is the one that is honored.

    only if your marker table is full you have to erase that sector.

    this greatly enhances your FLASH's lifetime. works for E2PROM emulation too.

    There are some caveats though... if you need to erase, you should consider what happens if that thing resets or power fails

    just before a valid marker could be written.

    If an invalid marker turns your device into a paperweight, you might consider some form of double buffering.

    Cheers, Roger