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Altera_Forum
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19 years ago

I encounter a sopcbuilder problem

while using new component wizard:

Error: command "quartus_map --generate_hdl_interface=D:/altera/quartus60/work/NL6448BC20_controller_prototype/ce_temp_directory/read1_master.v ce_temp_directory/ce_temp_quartus_project" returned 3

Error (10670): Verilog HDL or VHDL error: cannot create XML design interface for design file D:/altera/quartus60/work/NL6448BC20_controller_prototype/ce_temp_directory/read1_master.v. File: D:/altera/quartus60/work/NL6448BC20_controller_prototype/ce_temp_directory/read1_master.v Line: 1

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

Error: Processing ended: Wed Mar 14 10:54:26 2007

Error: Elapsed time: 00:00:01

Error: D:/altera/quartus60/work/NL6448BC20_controller_prototype/ce_temp_directory/read1_master.v.xml does not exist

I do not know why.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    --- Quote Start ---

    originally posted by guoyu@Mar 13 2007, 09:21 PM

    while using new component wizard:

    error: command "quartus_map --generate_hdl_interface=d:/altera/quartus60/work/nl6448bc20_controller_prototype/ce_temp_directory/read1_master.v ce_temp_directory/ce_temp_quartus_project" returned 3

    error (10670): verilog hdl or vhdl error: cannot create xml design interface for design file d:/altera/quartus60/work/nl6448bc20_controller_prototype/ce_temp_directory/read1_master.v. file: d:/altera/quartus60/work/nl6448bc20_controller_prototype/ce_temp_directory/read1_master.v line: 1

    error: quartus ii analysis & synthesis was unsuccessful. 1 error, 0 warnings

    error: processing ended: wed mar 14 10:54:26 2007

    error: elapsed time: 00:00:01

    error: d:/altera/quartus60/work/nl6448bc20_controller_prototype/ce_temp_directory/read1_master.v.xml does not exist

    i do not know why.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=22266)

    --- quote end ---

    --- Quote End ---

    Do you use parameters in your HDL by any chance? If so can you copy and paste them into this post. I&#39;ve seen this message before when you have a parameter based on another parameter.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    The problem with parameters inside your verilog source during sopc component generation is not new (but mostly fixed)

    if you add a source.v as a hdl file inside the sopc component editor then in priviously versions you couldn&#39;t have a struct like

    mymodule ( .... );

    parameter EnableLCD = 1;

    quartus itself can deal with such parameters, but during sopc component editor this was not possible. i had to remove such parameters, do the sopc job and then re-add the parameter.

    Quartus 6.1 and Quartus 7.0 can handle such parameters.