I encounter a sopcbuilder problem

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originally posted by guoyu@Mar 13 2007, 09:21 PM

while using new component wizard:

error: command "quartus_map --generate_hdl_interface=d:/altera/quartus60/work/nl6448bc20_controller_prototype/ce_temp_directory/read1_master.v ce_temp_directory/ce_temp_quartus_project" returned 3

error (10670): verilog hdl or vhdl error: cannot create xml design interface for design file d:/altera/quartus60/work/nl6448bc20_controller_prototype/ce_temp_directory/read1_master.v. file: d:/altera/quartus60/work/nl6448bc20_controller_prototype/ce_temp_directory/read1_master.v line: 1

error: quartus ii analysis & synthesis was unsuccessful. 1 error, 0 warnings

error: processing ended: wed mar 14 10:54:26 2007

error: elapsed time: 00:00:01

error: d:/altera/quartus60/work/nl6448bc20_controller_prototype/ce_temp_directory/read1_master.v.xml does not exist

i do not know why.

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Do you use parameters in your HDL by any chance? If so can you copy and paste them into this post. I&#39;ve seen this message before when you have a parameter based on another parameter.