Honored ContributorHi,
When I run debug (custom board), IDE writes: Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: FAILED Leaving target processor paused ...and I can't run my program (nothing else happen). What's wrong? Thank You for any ideas.
Honored ContributorFirst, load sof of your board with quartus programmer.
Honored ContributorHi,
Make sure you downloaded the right NIOS into your board. Make sure the clock-frequency is not too high, else you could having problems with your memory Cheers, DannyHonored ContributorThank yuo for yours suggestions:
hippo - the pof is on EPCS4, when I try load sof by flash programmer, the same situation, than when I try debug application (Resetting and pausing target processor: FAILED Leaving target processor paused) dannyjacobs - I think, I downoloaded the right NIOS in my board. Clock freq = 33.33MHz, Reset Nios pin is no drive (with default value VCC). About memory - I'll try use only OnChip memory and smallest NIOS application. Thank youHonored ContributorOne question: how the JTAG "Resetting and pausing target processor"? It happens inside the processor, or I have to connect any signal to nios reset pin?
Honored ContributorThe reset of nios2 can not be VCC. You must supply a reset pulse.
Honored ContributorI agree, it's no so good about not drive nios reset pin, but in our preview board it works - after ConfigDone, Nios starts from reset address.
But, if no driving reset pin maby cause in my case? Probably JTAG is reseting NIOS internally.Honored ContributorI have had this problem for over a year now. It is maddening. I can have a perfectly good system set up on a cyclone development board, hardware and software, and it runs perfectly. Download hardware image from USB Blaster, store it in flash, it doesn't matter. I can debug with the NIOSII IDE no problem. But !!!!
If I recompile the hardware in Quartus about 50% of the time I get the mesage you see from the NIOSII IDE. I have then gone back to Quartus and changed some compiler optimization ( seems to be a different one every time ) and recompile and get a hardware image that works again. My only theory is I'm introducing a timing error into the JTAG UART component that does not allow the NIOSII IDE to communicate with the NIOSII core. Any thoughts??? I'm using 5.0 and don't have access to 5.1 at the moment.Honored ContributorI had the same problem with version 5.0, even my design was working. I just restarted the debug session and it was working. Since I have upgraded to IDE and Quartus 5.1 I dont have this problem anymore...
Regards
