Forum Discussion
Altera_Forum
Honored Contributor
19 years agoI have had this problem for over a year now. It is maddening. I can have a perfectly good system set up on a cyclone development board, hardware and software, and it runs perfectly. Download hardware image from USB Blaster, store it in flash, it doesn't matter. I can debug with the NIOSII IDE no problem. But !!!!
If I recompile the hardware in Quartus about 50% of the time I get the mesage you see from the NIOSII IDE. I have then gone back to Quartus and changed some compiler optimization ( seems to be a different one every time ) and recompile and get a hardware image that works again. My only theory is I'm introducing a timing error into the JTAG UART component that does not allow the NIOSII IDE to communicate with the NIOSII core. Any thoughts??? I'm using 5.0 and don't have access to 5.1 at the moment.