Forum Discussion
New ContributorHyperRAM Hyperbus options for Agilex
In migrating a Xilinx design :
We are looking to use a A5E A 007 B23B device with a NIOS-V or other RISCV soft core.
Because we need to use the HSIO pins for ~ 20 pairs of LVDS, and the entireHSIO bank (96 wide) having to be at 1.3V to support LVDS mean that we cannot use the internal LPDDR4 memory controller.
Please confirm my understanding - that although the 96 wide I/O bank can be split into two functional sub banks (2A, 2B etc) (to support say, LPDDR4(16 bit), and something else , that we CANNOT split the VCCIO-BANK between the two sub banks ? (to have 1.1V for LPDDR4 and 1.3V for LVDS)
The projects do not need much memory- a 64 Mbit HyperRAM device hanging from 1.8V HVIO would do the job (perhaps max clock 125 MHz on HVIO ?)
What instantiable cores do ALtera have in the war chest for HyperRAM? There is a 3rd party Hyperbus controller IP but we wont want to spend $10,000 on it, as moving from a cheaper Xilinx device to a less competitive Altera device is already a big job and we do not think it deserves having that much more money spent on it. (Efinix have a free Hyperbus core, Xilinx have a free Hyperbus core....)
Regards
Glen.
2 Replies
glenenglish@ ai_responder
referring to : document 813934
The documentation says "if all the I/O standards support the VCCIO_PIO of the I/O bank."
The language suggests and implies that there is a single I/O bank VCCIO_PIO...
It should read "if the I/O standards support the VCCIO_PIO of the I/O sub-bank."
This should be re written to improve understanding.
In Pin Planner , I see there are separate VCCPIO T and B pins. OK.
According to the interface designer, the LPDDR4 16 bit (single bank) and the fabric (non HPS) solution CANNOT fit in top or bottom (T or B bank) . (ref clock and cal res constraints and # pins) . needs a whole I/O bank.
ai_responderCommunity Manager
Good questions, Glen — and the good news is your core premise about VCCIO needs correcting in your favour.
1. HSIO Sub-bank VCCIO Independence — you CAN split voltages between sub-banks
Your assumption that the entire 96-pin HSIO bank must run at a single VCCIO is incorrect. The sub-banks are electrically independent:
For Agilex 5 devices, the board must supply each HSIO sub-bank with one VCCIO_PIO voltage level for every VCCIO_PIO pin in that sub-bank. Each HSIO sub-bank is powered by the VCCIO_PIO pins of that sub-bank and is independent of the VCCIO_PIO pins of other HSIO sub-banks. Device Design Guidelines: Agilex™ 5 FPGAs and SoCs Each I/O bank has two sub-banks, and each sub-bank has its own PLL, DPA and SERDES circuitries, and individual VCCIO_PIO voltage rail. I/O Standard Selection and I/O Bank Supply Compatibility Check
The design guideline checklist is explicit: place HSIO pins that share voltage levels in the same I/O sub-bank Device Design Guidelines: Agilex™ 5 FPGAs and SoCs — which directly implies different sub-banks may operate at different voltages.So practically for your A5E 007 B23B design:
- Sub-bank 2A at 1.1 V → LPDDR4 (16-bit interface, ~38-40 pins, fits within the 48-pin sub-bank limit)
- Sub-bank 2B at 1.3 V → 20 LVDS TX pairs (40 pins, also within the 48-pin sub-bank limit)
One constraint to be aware of: each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-bank is operating in PHYLITE mode or GPIO mode. Otherwise, you must supply VCCIO_PIO with a ±3% voltage supply tolerance. Agilex® 5 FPGAs and SoCs Device Data Sheet For the LPDDR4 sub-bank in EMIF mode, keep the regulator tolerance to ±3%. Also confirm in Quartus Prime Pin Planner that the LPDDR4 16-bit interface pins fit within a single sub-bank for your specific package — EMIF can only be implemented on HSIO bank; EMIF is not supported on HVIO bank. Device Design Guidelines: Agilex™ 5 FPGAs and SoCsSo your LPDDR4 approach is not necessarily blocked — revisit pin planning with this understanding before abandoning it.
2. HVIO Clock Frequency for HyperRAM
For the HVIO bank System PLL reference clock input, the data sheet specifies:
Clock input frequency (FREF), powered by VCCIO_HVIO: Min = 25 MHz, Max = 125 MHz. Agilex® 5 FPGAs and SoCs Device Data Sheet
Your 125 MHz estimate for the HyperRAM clock on HVIO is consistent with the HVIO reference clock ceiling. A HyperRAM device running at or below 125 MHz on HVIO pins at 1.8 V is a reasonable target.3. HyperRAM IP for Agilex 5
There is a third-party "HyperRAM Controller" IP listed in the Altera partner ecosystem (Silicon Proven IP for Altera Devices). Key characteristics:
- Memory clock rate up to 250 MHz. HyperRAM Controller (Silicon Proven IP for Altera Devices)
- Supports 8-bit and 16-bit data buses, RWDS read/write data strobes, AXI4 memory-mapped interface for data, and APB for control. HyperRAM Controller (Silicon Proven IP for Altera Devices)
- Supports Linear Burst, Hybrid Burst, and Wrap Burst. HyperRAM Controller (Silicon Proven IP for Altera Devices)
- Compatible with W958D6NW, W958D6NKY, W956x8MBYA, and W955D8MBYA HyperRAM devices from Winbond. HyperRAM Controller (Silicon Proven IP for Altera Devices)
- Latest Quartus version supported: 24.3.1. HyperRAM Controller (Silicon Proven IP for Altera Devices)
- Delivered with SV/UVM testbench, behavioral PHY model, and a validated FPGA PHY reference design for rapid bring-up. HyperRAM Controller (Silicon Proven IP for Altera Devices)
- No design examples available as a separate free download. HyperRAM Controller (Silicon Proven IP for Altera Devices)
- An evaluation license is available. HyperRAM Controller (Silicon Proven IP for Altera Devices)
There is also a Jedec xSPI Controller IP in the Altera partner ecosystem that includes HyperRAM support: it operates with NOR, NAND, and HyperRAM devices from multiple vendors, and is compatible with Winbond, Adesto, Micron, Macronix, Cypress, and other similar devices. Jedec xSPI Controller (Silicon Proven IP for Altera Devices) That may be worth evaluating as an alternative at a different price point.
Altera does not currently list a first-party free HyperRAM IP equivalent to what Efinix or AMD/Xilinx offer — the options available are these partner/third-party cores. The evaluation license on the HyperRAM Controller IP lets you validate integration before committing to purchase, which is worth doing alongside the xSPI option to compare pricing.
Bottom line: revisit your HSIO pin plan — the sub-bank voltage independence may well let you keep LPDDR4 and LVDS coexisting on the same HSIO bank, which could simplify the overall BOM significantly compared to going the HyperRAM route.
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Thank you very much.
