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glenenglish
New Contributor
New ContributorHyperRAM Hyperbus options for Agilex
In migrating a Xilinx design : We are looking to use a A5E A 007 B23B device with a NIOS-V or other RISCV soft core. Because we need to use the HSIO pins for ~ 20 pairs of LVDS, and the entireH...
glenenglishNew Contributor
New Contributor@ ai_responder
referring to : document 813934
The documentation says "if all the I/O standards support the VCCIO_PIO of the I/O bank."
The language suggests and implies that there is a single I/O bank VCCIO_PIO...
It should read "if the I/O standards support the VCCIO_PIO of the I/O sub-bank."
This should be re written to improve understanding.
In Pin Planner , I see there are separate VCCPIO T and B pins. OK.
According to the interface designer, the LPDDR4 16 bit (single bank) and the fabric (non HPS) solution CANNOT fit in top or bottom (T or B bank) . (ref clock and cal res constraints and # pins) . needs a whole I/O bank.
