Altera_Forum
Honored Contributor
21 years agoHow to share signals on Avalon bus ?
Hi all,
after updating (Quartus II to version 4.2 and NIOS to 1.1) my CPU didn't run anymore due to obscure reasons (e.g. bit swapped addresses on some ports). That's why I've tried to completely reconstruct my cpu in this new environment. I used now 'create new component' instead of 'interface to user logic' to generate parts of my original device. It seems that it is now up to SOPC builder to decide which signals are shared on avalon bus and which not. Even if same timing is set and same interface name is used, SOPC builder generates shared byteenables_n but unshared write_n and read_n signals (CSn is of course never shared to guarantee single targets). How can I force shared avalon signals in 'create new component'? Do I have to use or-gates to merge unshared signals to a single signal? Thanks in advance Mike