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Altera_Forum
Honored Contributor
21 years agoHow to share signals on Avalon bus ?
Hi all, after updating (Quartus II to version 4.2 and NIOS to 1.1) my CPU didn't run anymore due to obscure reasons (e.g. bit swapped addresses on some ports). That's why I've tried to...
Altera_Forum
Honored Contributor
21 years agoSorry to hear that you're having trouble. Three options for you:
1. AND/OR the signals together as you desire. In reality, this may be the best option. There shouldn't (please tell me if there is) a problem with always sharing address/data/chipselect per tri-state bridge. 2. Edit the .ptf file of the component you made with component builder and turn on "is_shared" in the relevant SLAVE signal sections. A signal that 'is_shared = "1"' will be shared per tri-state bridge. 3. Use the old interface to user-logic with all of its lovely quirks and limitations. Its still there, located in the 'legacy components' folder of SOPC Builder. After discussing this with some of our designers I think that the way its done now is actually all right, if not 100% optimial & whiz-bang -- the whole "is shared thing", from the perspective of the component builder and designing user-logic, is a bit skewed as the component builder has no knowledge if how multiple things will be later connected to a single tri-state bridge by the user. If you have any other problems or comments feel free to let us know!